1. Field of the Invention
The invention relates to a method for addressing a memory area in a memory circuit. The invention also relates to an address decoding circuit for decoding an address for response (as a function of the address) of a regular memory area or of a redundant memory area. The invention furthermore relates to an integrated circuit having an address decoding circuit.
2. Description of the Related Art
In addition to regular memory circuits, integrated memory circuits generally have redundant memory areas which can be connected by cutting through or not cutting through fuses after completion of the processing of the wafer. Each redundant memory area has an associated fuse memory unit with a number of fuses, in which the address of the regular memory area to be replaced can be coded.
When a data access is made, if an address is applied which is coded in the fuse memory unit for a redundant memory area, then two signals are produced from the comparison of addresses and of the address information which is set in the fuse memory unit. Firstly, the redundant memory area which is associated with the corresponding fuse memory unit is activated on the basis of a redundancy activation signal for the current data access, and secondly, the activation of the regular memory area to be replaced is prevented. This is normally achieved with the aid of a deactivation signal which, for example, uses a switch to prevent the regular memory area from being driven (for example, preventing the activation of the corresponding word line).
The check to determine whether the applied address corresponds to the address stored in the fuse memory unit requires a longer time period than the processing of the address signals for addressing the regular memory areas. The evaluation of the redundancy information thus represents a critical path because the signal path through the redundant address decoder that is formed with the aid of the fuse memory element takes longer than the signal path through the regular address decoder. A delay element must therefore be provided such that the activation of an associated driver circuit for addressing the regular and redundant memory areas which are addressed by the address takes place a specific time period after the deactivation signal. If the deactivation signal indicates only after the activation of the delayed access signal that the regular memory area should not be activated, then the incorrect regular memory area will be activated for a short time, which leads to increased power consumption and/or to the memory circuit behaving incorrectly.
In the past, the critical path delay has been minimized as much as possible. However, both the rising edge and the falling edge of the deactivation signal must be set as well as possible, which always represents a compromise, since separate optimization of the rising edge and of the falling edge would lead to better solutions.